In the current integrated circuits (ICs) business, whose total world market now is in excess of $100 billion, all of the ICs are manufactured using a 2-dimensional (2-D) technology. This means that all the IC chips on a single crystal (SC) silicon (Si) wafer use various types of devices, such as transistors and diodes, laid out on the Si surface in a 2-D manner. In such a manufacturing technology, epitaxial layers of Si grown on the SC Si wafer substrate are used commonly. These are SC Si layers having the same crystal orientation as that of bulk SC Si wafer. The crystal structure of the epitaxial layers, as well as that of the bulk Si wafer, is required to be near perfect for achieving excellent and reproducible device characteristics. This goal has been achieved, and that is why the entire microelectronic industry has continued to grow according to Moore""s Law (Ref. 1), and is doing quite well indeed.
Moore""s Law (Ref. 1; ibid) has guided the entire microelectronic industry very well so far. However, the entire microelectronic industry consists of, and Moore""s Law applies to, monolithic Si ICs only, in which all the devices are laid out in a 2-dimensional manner in a SC of Si. Such ICs are known popularly as chips, and they can also be referred to as 2D-Si-ICs. Another key point to remember is that these ICs use primarily electrical signals to perform all the functions. For faster electrical functions, eg, in the microwave regime, and for performing optical functions, devices made on SC compound semiconductor wafers and films are needed. Moore""s Law (Ref. 1; ibid) does not apply to compound semiconductor ICs, nor to the combination of monolithic Si-compound semiconductor ICs.
One of the key features of Moore""s Law (Ref. 1; ibid) is that it predicts the rate of growth of the total number of devices per chip. This requires, and it also forecasts, the rate of decrease of minimum geometries of the devices and interconnects. Consequently these Si ICs, have grown continually in complexity. They have had an ever increasing device density, and they have been fabricated with ever decreasing sizes of the device and interconnect geometries. However, due to the fundamental limits of the materials and the associated technologies, this cannot go on forever. Dr. Moore (Ref. 1; ibid) has reviewed various other factors also, and has concluded that his law will cease to be valid before too long. While no definite limit has been established yet, it appears that the validity of Moore""s Law will cease at dimensions smaller than about 0.1 xcexcm.
The level of integration in Si ICs in terms of device density, however, can continue to be increased beyond the limit of Moore""s Law (Ref. 1; ibid), ie, beyond the 2-D limit of 0.1 xcexcm. This can be achieved even without scaling the device and interconnect geometries, by invoking device fabrication in the third dimension, viz, by manufacturing 3-dimensional (3-D) ICs. This would enhance the device density, and hence the functionality and performance of the Si ICs, both in the present regime where Moore""s Law is valid, and also beyond its limit of validity for the 2D-Si-ICs. Thus, the mandatory necessity for continued device and interconnect scaling to achieve an ever increasing number of devices per chip with time according to Moore""s Law (Ref. 1; ibid), and to keep on pushing the manufacturing technologies to the limit, is obviated by the 3D-Si-ICs. However, to manufacture the truly 3-dimensional ICs, viz, 3D-Si-ICs, SC films of Si need to be grown on the amorphous (AM) silicon-di-oxide (SiO2) layers or films (these two words, viz, layers or films, are being used interchangeably in this patent write-up, and also in the literature). No production worthy technology is available yet to do this. The SiO2 films, as it is well-known, are an inherent part of the structure of the 2D-Si-ICs.
The requirement to grow good SC films of Si on AM SiO2 films, is similar to that of the bulk SC Si wafers. Their crystal perfection has to be free of any defects, so that the performance characteristics of the devices are excellent and reproducible all the time. Recrystallization of AM and polycrystalline Si (poly-Si) films deposited on AM SiO2 films, has been attempted in the past, but it has not produced good SC films of Si. This technique has given Si films, having small regions with different crystal orientations, and resulting in many grain boundaries. This type of film will produce devices with poor and varying electrical characteristics within a chip, chip-to-chip, and wafer-to-wafer. No wonder that such a film has not yet been successful in producing the 3D-Si-ICs. This is evident from the fact that no such products are available so far in the microelectronic industry. So, the critical need to produce 3D-Si-ICs is to be able to fabricate devices on good SC films of Si grown reproducibly on AM SiO2, or other suitable insulator, eg, Si3N4, films used currently in the manufacturing of the 2D-Si-ICs.
One of the techniques attempted so far to grow SC films of Si on AM SiO2 films, has been to use epitaxial lateral overgrowth (ELO) technology. In this technology, seeding from the SC Si substrate is used to grow the epitaxial SC Si layers over SiO2 films (Ref. 2). However, this technology, though tried for over a decade, has not yet been successful either to grow good SC films of Si on SiO2 films reproducibly. Another drawback of the ELO technology is that it requires area on the chip for seeding purposes. This negates the advantage of 3D-Si-ICs over 2D-Si-ICs for increasing the device density, by taking away the valuable area for seeding which could have been used for devices. Other approaches to accomplish this, are wafer bonding and SIMOX (separation by implantation of oxygen). For a recent review, see Ref. 3. While these technologies have made good progress for SOI (silicon-on-insulator), they have not yet been found suitable for fabricating 3D-Si-ICs.
The invention described here relates to the fabrication of semiconductor devices in single crystal films grown on arrayed nucleation sites on amorphous and/or non-crystal surfaces. Henceforth, such new devices shall be referred to as SCANS devices. As an example, this invention will allow fabrication of SCANS devices in SC Si films grown selectively on AM SiO2 films of a processed ULSIC wafer. These SC Si films can have any desired orientation of crystal planes, eg, (100), (111), etc. Further, this invention allows fabrication of different types of SCANS devices in SC Si films having different crystallographic planes/structures, grown simultaneously by in-situ selective growth in their respective regions of AM substrates.
Devices for performing optical functions, and for faster electrical functions, eg, in the microwave regime, are better performed with devices fabricated in SC compound semiconductors (eg, GaAs, GaAlAs, GaP, etc) than those fabricated in SC Si. Therefore, it is also of interest to grow SC compound semiconductor films on SiO2 surfaces of ULSICs. The SCANS devices fabricated in such compound semiconductor films, can be used for performing optical functions, and for faster electrical functions, eg, in the microwave regime. The invention described here enables this technology also. Combining the best of both the worlds of Si and compound semiconductor ICs leads to ultra performance ICs (UPICs) (Ref. 4). Thus, the maximum functionality, reliability and low power of Si ICs can be integrated monolithically with the unique performance (eg, optical and microwave) capabilities of the compound semiconductor ICs to produce UPICs. The UPICs are the ultimate in ICs known to mankind (Ref. 4; ibid).
No production worthy technologies to grow SC films of Si and compound semiconductors on AM surfaces are available so far. However, the invention described here enables these technologies for the fabrication of 3D-Si-ICs and UPICs. The invention described here can also be used to enhance the performance and the yield of the current 2D-Si-ICs which are already in manufacturing. The poly-Si films used now in the Si-gate technology, can be replaced with SC Si films grown with this invention on arrayed nucleation sites on AM SiO2 or Si3N4 films. The process control and the properties of such SC Si films will be superior to those with poly-Si films. As an example, the electrical sheet resistivity of doped poly-Si films of about 15 xcexa9/square can be reduced to about 5 xcexa9/square by using SC Si films grown with this invention. This electrical sheet resistivity can be reduced further by the well-known (self-aligned silicide) technology. Further the reliability of the devices with such SC Si films, will be superior to that with poly-Si films. This is due to the improved Sixe2x80x94SiO2 interface with the SC Si films, as compared to that with poly-Si films.
The purpose of the present invention is to allow the fabrication of devices with an innovative technology, which enables the growth and deposition of SC layers of any desired orientation of almost any material (semiconductor, metal or insulator) on an array of nucleation sites on AM and/or non-single crystal surface. More importantly, this technology will produce SC Si layers of any desired orientation on an AM layer, eg, SiO2 or Si3N4. More specifically, it will allow growth of SC Si films of (100) crystal orientation on SiO2, which is the most desirable orientation for the manufacturing of complementary metal-oxide-semiconductor (CMOS) ICs. The CMOS ICs are the largest and the most important segment of the entire IC industry. Thus, as an example, the growth of SC Si films with (100) orientation on SiO2 or Si3N4 films on processed 2D-Si-IC wafers, will enable the fabrication of CMOS 3D-Si-ICs. The need to continue scaling the minimum geometries in the conventional 2D-Si-ICs according to Moore""s Law (Ref. 1; ibid), can be stemmed by the 3D-Si-ICs. Moreover, the device densities can continue to be increased with the 3D-Si-ICs even beyond the validity of Moore""s Law (Ref. 1; ibid), without pushing the limits of photolithography technology.
The present invention also enables the growth of SC compound semiconductor (eg, GaAs, GaAlAs, GaP, etc) films on SiO2 or Si3N4 on processed Si wafers. Thus, the optical functions can be performed monolithically with the electrical functions of the ULSIC chips, producing newer chips which have not yet been possible so far in the microelectronic industry. Also, MMICs (Monolithic Microwave ICs) can be fabricated monolithically on Si ULSICs. These technologies will allow system-on-a-chip type of microprocessor chips to be manufactured, which will be superior telecommunication and computer ICs than any kind available today.
The key feature of the present invention is to create arrayed nucleation sites in the AM layers, eg, SiO2 on an IC wafer, by high-dose implantation through a SC mask having appropriate channeling directions at the desired lattice constants. Wherever these nucleation sites are created, they act as affinity sites for the incoming atoms to deposit on them only. These sites encourage to rebuild the crystal matrix at the right places, and they discourage the nucleation at the wrong places on the surface of the AM substrate. Thus, SC layers will be deposited selectively in the regions having the arrayed nucleation sites. On those regions of the AM substrate, where these nucleation sites are not created, the incoming atoms will either not deposit at all, or they will deposit to give a non-single crystal layer. By adjusting the deposition process conditions, the deposition of the non-single crystal layers in the latter regions can be eliminated altogether, while retaining the SC deposition in the previous regions having the arrayed nucleation sites. This is known as the selective deposition process. It is practiced commonly in the industry, eg, for the selective deposition of Si.
The SC mask referred to above, and described in Ref. 6, is a thin membrane, a few microns thick, of a suitable single crystal material. It can be positioned on the desired regions by using, as an example, the step-and-repeat technology similar to a stepper used in photolithography for IC manufacturing. The desired implantations may be performed in apparatus of the Applicant""s inventions (Refs. 5 and 6).
Another key feature of this invention is, that the arrayed nucleation sites can be created in the AM layers, eg, SiO2 on an IC wafer, by either xe2x80x9cadditivexe2x80x9d or xe2x80x9csubtractivexe2x80x9d methods. The xe2x80x9cadditivexe2x80x9d method is defined to be the method when the nucleation sites are created on or near the AM surface by xe2x80x9caddingxe2x80x9d the desired species. This is accomplished by depositing the desired species, by a channeling type of ion implantation through the SC mask, to give the arrayed nucleation sites on or near the AM surface. Such arrayed nucleation sites correspond to the chosen crystal structure of the SC mask. FIG. 1 shows the distribution of the implanted species, and their differentiated density in the X-direction (lateral, spaced apart across the surface), and Z-direction (depth, from the surface into the bulk) of the AM substrate. The distribution of the implanted species is Gaussian in both directions. The depth of the peak distribution in the Z-direction is termed as the projected range, and is denoted by rp. Its value depends on various factors, eg, the energy and the type of incoming ion, the substrate, and the angle of the implantation. As an example, the rp of Si28 ions of 20-25 KeV energy in AM SiO2substrate at normal incidence, is about 220-270 Axc2x0. The peak of the Gaussian at rp can be exposed by appropriate etching procedures, eg, by reactive ion etching (RIE).
The xe2x80x9csubtractivexe2x80x9d method relies on knocking off an atom from the host AM substrate from each of the arrayed affinity sites defined by the SC mask, by a suitable process, such as sputter etching or chemical removal. This is illustrated for an AM SiO2 substrate in FIG. 2 . FIG. 2(a) shows two xe2x80x9cSiO4xe2x80x9d tetrahedra of AM SiO2 linked together. The first tetrathedron has Si1 at the center, linked with four oxygen atoms labelled as O11, O12, O13 and O14. Similarly, the second tetrathedron has Si2 at the center, linked with four oxygen atoms labelled as O21, O22, O23 and O24. The oxygen atom linking the two tetrahedra is shared between them, and it is labelled as O14/O22. When, as an example, an argon (Ar) ion is implanted through the SC mask, it can knock off the oxygen atom from one of the tetrahedra of the AM SiO2 substrate. This is shown in FIG. 2(b), in which O11 is removed, leaving one of the chemical bonds of Si1 open. This acts as a nucleation site for the incoming Si during the subsequent epitaxial growth. As an example, Ar40 ions of 20-25 KeV energy can be used to create the affinity sites by the xe2x80x9csubtractivexe2x80x9d method employing sputter etching. For these Ar40 ions, the rp in AM SiO2 substrate at normal incidence, is about 180-240 Axc2x0. Similarly, F19 can be used with H2 flowing at the surface of the AM SiO2 substrate, to create the affinity sites by the xe2x80x9csubtractivexe2x80x9d method employing chemical etching.
An example for growing SCAN films of Si having the (100) crystal structure is as follows. A thin SC mask of (100) Si, 7-12 xcexcm thick, can be used through which Si ions can be implanted in the channeling direction to create the nucleation sites on a SiO2 layer of a Si IC wafer. The energy of implanting ions is preferably low, and the dose is preferably high. Typical energy is about 20 to 25 KeV, and the Si implantation dose can be about 1014 to 1016/cm2. Such a SC mask may be cooled to liquid nitrogen temperature to retard, if not prevent, its amorphization at certain high dosages of the implant. Subsequent to this creation of nucleation sites, epitaxial Si is grown on such a SiO2surface by CVD of Si. The chemicals used for this epitaxial growth can be SiCl4, SiHCl3, SiH2Cl2 or SiH4 in H2 carrier gas in a conventional epi reactor, or, once again, the Applicant""s invention (Ref. 5; ibid) can be used. Similarly, the arrayed nucleation sites for other materials can be used by using an appropriate mask for the desired single crystal orientation, and implanting and depositing the desired nucleation species through such a mask. Subsequent to this, epitaxial growth for the desired SC can be employed.
The present invention also enables large area semiconductor films to be grown on AM glass substrates. They can be used for producing large area solar cells of high efficiency. This will enable electric power to be generated from sunlight economically. Such solar cells will become more and more important to mankind with the passage of time, as the natural fossil fuels are depleted in the world. Another important feature of the present invention is that it will allow the fabrication of large area flat panel displays and TV, which will be superior to those currently known.
The unique capability of the present invention is to enable the selective growth of SC films of almost any material, having the desired crystal structure, on suitable AM substrates. Thus, it can also be utilized to grow SC layers of high Tc superconductors on AM substrates. This capability will allow high critical currents to be achieved in high Tc superconductors, which is an important limitation in today""s technology. Therefore, such high Tc superconductor films can be also used for the interconnect applications in high efficiency large area solar cells, flat panel displays, TVs, Si-ICs, and UPICs.